[132] ....the early
1980s, Marshall Space Flight Center began studying a Block II
controller design because it was becoming impossible to find parts
and programmers for the late 1960s components of the Block
I183. The revised computer uses a Motorola 68000 32-bit
microprocessor. When selected, it was clearly the state of the
art. Instead of plated wire, a CMOS-type semiconductor
random-access memory is used. Finally, the software is written in
the high-level programming language, C. Such a computer reflects
the current design and components of a ground-based, powerful
digital control system. The C language is also known as an
excellent tool for software systems development. In fact, the UNIX
operating system is coded in it.
Aside from the processor change, the Block
II's memory was increased to 64K words. Therefore, the entire
controller software, including preflight routines, can be loaded
at one time. Semiconductor memories have the advantages of high
speed, lower power consumption, and higher density than core, but
lack core memory's ability to retain data when power is shut off.
Reliability of the memory in the Block II computer was assured by
replicating the 64K and providing a three-tier power
supply184. Both Channel A and Channel B have two sets of 64K
memories, each loaded with identical software. Failure in one
causes a switch-over to the other. This protects against hardware
failures in the memory chips. The three tiers of power protect
against losing memory. The first level of power is the standard
115-volt primary supply. If it fails, a pair of 28-volt backup
supplies, one for each channel, is available from other components
of the system. Last, a battery backup, standard on most
earth-based computer systems, can preserve memory but not run the
processor.
The significance of the evolution to Block
II engine controllers is that they represent the first use of
semiconductor memories and microprocessors in a life-critical
component of a manned spacecraft. Honeywell scheduled delivery of
a breadboard version suitable for testing in mid-1985. The new
controller is physically the same length and width, so it fits the
old mounting. The depth is expected to be somewhat less. When the
first of these computers flies on a Shuttle, NASA will have
skipped from 1968 computer technology to 1982 technology in one
leap.
IBM's new version of the AP-101 (the F)
incorporates some of the same advantages gained by the new
technology of the engine controllers. Increasing the memory to
256K words means that the ascent, on-orbit, and descent software
can be fitted into the memory all at once. (This is not likely to
happen, however, because of the pressing need to improve the crew
interfaces and expand existing functions.) Higher component
density allows the CPU and IOP to be fitted into one box roughly
the size and weight of either of their predecessors. Execution
speed is now accelerated to nearly 1 million operations per
second, twice the original value. In essence, NASA has finally
acquired the power and capability it wanted in 1972, before the
software requirements showed the inadequacy of the original
AP-101.
[133] As in the engine
controllers, the memory in the AP-101F is made of semiconductors.
Power can be applied to the memory even when the central processor
is shut down so as to keep the stored programs from disappearing.
A commercially available error detection and correcting chip is
included to constantly scan the memory and correct single bit
errors. These precautions help eliminate the disadvantage of
volatility while still preserving the size, power, and weight
advantages of using semiconductors over core memories
185.
