Computers in Spaceflight: The NASA Experience

- Chapter Four -
- Computers in the Space Shuttle Avionics System -
The DPS hardware configuration
[93] The DPS hardware in the shuttle avionics system consists of four major components: general-purpose computers, the data bus network, the multifunction cathode ray tube display system, and the mass memory units. Each is a substantial improvement over similar systems in any previous spacecraft. Together, they are a model for future avionics developments.
General-Purpose Computers
NASA uses five general-purpose computers in the Shuttle. Each one is an IBM AP-101 central processing unit (CPU) coupled with a custom-built input/output processor (IOP). The AP-101 has the same type of registers and architecture used in the IBM System 360 and throughout the 4Pi series29. IBM announced the 4Pi in 1966, so by the early 1970s, when Shuttle procurement was complete, the machine had had extensive operational use30. The AP-101 version, which is an upgraded AP-1, has since been used in the B-52 and B-1B military aircraft and the F-8 digital fly-by-wire experimental aircraft. The central processor in each case is the same, but the IOP is adapted to the particular application.
Although one of the reasons for choosing the AP-101 was its familiar instruction set, some modifications were necessary for the Shuttle version. Since the execution of instructions is dependent on microcode, rather than hardware only, the instruction set could be changed somewhat. Microcode is a set of primitives that can be combined to create new logic paths in the hardware. The AP-101 has room for up to 2,048 microinstructions, 48 bits in length31.

Figure 4-2.
Figure 4-2. A block diagram of the hardware that makes up the Shuttle Data Processing System. The fifth computer is the Backup Flight System computer.


[95] Box 4-1: IBM AP-101 Central Processor and Memory Hardware
Shuttle computers make extensive use of standard ICs. The AP-101 is built using transistor-transistor logic (TTL) semiconductor circuits as the basic building block. The TTL gates are arranged in medium-scale integration (MSI) and large-scale integration (LSI) configurations32. The circuits are on boards that can be interchanged as units.
The AP-101 uses a variety of word sizes. Instructions can be either 16 or 32 bits in length. Fixed-point arithmetic, done using fractional numbers stored in two's complement form, also uses 16- and 32-bit lengths. Floating-point arithmetic is done with 32-, 40- and 64-bit words, although the latter are limited to addition and subtraction33. Instructions using floating-point take longer to execute than fixed-point arithmetic, and adding is still faster than multiplying; but average speed for the machine is 480,000 instructions per second, compared with 7,000 instructions per second in the Gemini computer34.
The CPU registers are in three groups. Two sets of eight 32-bit registers are available for fixed-point arithmetic. One set of eight 32-bit registers is for floating point operations35. Semiconductor memories are used in the registers instead of discrete components. As a result, the registers are faster than those used on Gemini and Apollo and, since they are available in large sets, can be used to store intermediate results of calculations without having to access core memory. Thus, processing is accelerated and achieves the performance noted above36.
A program status word (PSW), 64 bits in length, is used to help control interrupts. The PSW contains information such as the next instruction address, current condition code, and any system masks for interrupts37. It has to be updated every instruction to stay current38. Since the AP-101 allows 61 different interrupt conditions divided into 20 priority levels, it is necessary to have an accurate indication of where a program left off when interrupted39. At any given time, several programs are likely to be in a suspended state.
The processor has more than one level of addressing. The common 16-bit address can only directly address 64K words, which was the original memory size of the AP-101. The addressing is extended by replacing the highest order bit with 4 bits from the program status word that indicate which sector of memory to access40. This is similar to the scheme used in the AGC when its memory had to be expanded. This configuration allows 131,072 full words (32-bit words) to be addressed. The architecture permits addressing up to 262,144 full words, so memory can be expanded without affecting the processor's design41.
[96] Due to packaging considerations, the core memory is located partly in the central processor and partly in the IOP (they are boxed separately). However, it is still considered as a single unit for addressing and access. The entire memory is shared, not just the portion located in the individual boxes. Originally, 40K of core were in the CPU and 24K in the IOP. The memory is organized into modules with 18-bit half words. These contain 16 bits of data, a parity bit, and a storage protect bit to prevent unintentional alteration of the data42. The original memory modules contained 8K half words, so 6 were needed in the IOP and 10 in the CPU to store 64K full words. Later memory expansion consisted of replacing the CPU memory modules with double-density modules, in which twice the cores are in the same size container as a single-density module43. So by the first flight, the Shuttle computer memories were 104K words or 106,496 full words of 32 bits. The memory access time is 400 nanoseconds, quite fast for core.

The eventual Shuttle instruction set contained 154 instructions defined within that 2K memory. However, the expected advantages of the flexibility of microcoding, which influenced the decision to select the AP-101, were lessened by the fact that at least six of the new instructions either did not work properly or performed insufficiently44. One NASA manager said that the microcoding was bungled by "the ones and zeroes artists" (referring to the binary numbered nature of microprograms) who apparently tried to do things the tricky way45.

NASA tried to correct its tendency to underestimate memory size, but was disappointed again on the Shuttle program. One requirement for memory was that it be large enough to contain all the programs necessary for a mission. Therefore, memory estimates became a regular part of preliminary design studies. Most estimates in the 1969 to 1971 period ranged around 28K words46. Rockwell International settled on 32K in its bid and won the contract partially because of that estimate47. NASA, trying to save itself from later difficulties, bought 64K of memory for each computer, hoping that doubling the estimate would be enough (despite memory increases in previous programs of several hundred percent)48. Unfortunately, the software grew to over 700K, requiring not only more computer memory, but the addition of mass memory units to hold programs that would not fit into the extended core. Parten said after this, "I don't know how you ensure proper memory size ahead of time, unless you're incredibly lucky"49.

From the standpoint of a spacecraft designer worried about power requirements, an interesting feature of the AP-101 memory is that only the module currently being accessed is at full power. If a memory module is used, it remains at full power for 20 microseconds. [97] If no further accesses are made in that interval, it automatically goes to medium power. If the entire computer is in standby mode, it goes to low power. An estimated 136 watts are saved by doing this switching50.

The memory can be altered in flight. The ground can uplink bursts of 64 16-bit halfwords at a time, which can replace data already in the specified addresses. The crew can also change up to six 32-bit words simultaneously by using their displays and keyboards. However, those changes must be hand keyed in hexadecimal.
The Shuttle's AP-101 contains one of the most extensive sets of self-testing hardware and software ever used in a flight computer. Its self-test hardware resides in the BITE, or built-in test equipment. When this is coupled with the self-test software, 95% of hardware failures can be detected by the machine itself 51, whereas the other 5% and potential software failures require the use of redundancy.
As evidenced by the component description given here, the IBM AP-101 is a fairly common computer architecture, easily understandable and programmable by anyone familiar with IBM's large commercial mainframes. The IOPS, bus system, and displays contain the characteristics that make the Shuttle DPS unique.
The IOPs and the Bus System
It is difficult to discuss the Shuttle's IOPs without also talking about the data bus network, because the former are designed to manage the latter. All subsystems on the spacecraft are connected redundantly to at least a pair of data buses. There are 24 of these buses, and the subsystems share them, using multiplexers to control the sharing. Eight of the 24 are "flight-critical data buses" that help fly the vehicle; 5 are used for intercomputer communication among the five general-purpose computers; 4 connect to the four display units; 2 run to the twin mass memory units; 2 more are "launch data buses," and connect to the Launch Processing System; 2 are used for payloads, and the final pair for instrumentation52. Each bus is individually controlled by a microprogrammed processor, essentially a small special-purpose computer, called a bus control element (BCE). The BCE can access memory and execute independent programs53. A twenty-fifth computer, the Master Sequence Controller, is used to control I/O flow on the 24 BCEs54. Thus, each IOP contains 25 dedicated computers. In addition, the IOP itself is basically a programmable processor with multiple functions. It shares main memory with the central processor. If a program affecting the IOP is initiated by the central processor, a direct memory access channel is opened to speed up reading core. That, however, creates contention for the memory [98] with the central processor and may have the effect of actually slowing down the system as a whole55.
One reason an IOP is needed is that the Shuttle computers transfer data internally in parallel along 18-bit buses. This means that one half word and its associated parity bit are moved from memory to the operation registers and back again all at once. However, data are transferred from orbiter subsystems to the IOP in serial form, one bit at a time. Of course, the serial data are at a high rate (1 megahertz), so transfer speed is not a concern. The conversion of serial data to parallel data is the function of the Multiplexer Interface Adapters in the IOP56. The Shuttle DPS also has 16 multiplexer/demultiplexers that convert parallel data to serial for output to the buses57.
Input and output to each computer is ultimately controlled in two modes: command and listen. In command mode (CM), signals sent from the host processor to subsystems connected to a bus controlled by a commanding BCE will actually effect the commands. In listen mode, the subsystems will ignore the command signals. In both cases input to the computer from any bus is listened to, but the computer's orders are obeyed only by the systems on the buses for which it is the commander. This moding capability means that a single computer can be assigned a set of buses different from another computer, thus spreading out the responsibilities and protecting against failure. It also means that each computer receives all input data all the time, so that it can take over from a failed computer immediately. This is especially important to the backup flight system. The set of controlled buses is called a "string." A typical string for a single computer might be a pair of flight critical buses, one intercomputer bus (always), a display bus, and a bus from the mass memory unit (MMU), payload, launch, and instrumentation group. The strings can be reconfigured by the crew in flight, which is done periodically as missions proceed through various phases.
Display Electronics
The Shuttle's display system, built by the Norden Division of United Technologies Corporation, is the most complex ever used on a flying machine and contains computers of its own. For the first time in a spacecraft, cathode ray tubes (CRTs) are used as the primary display medium, although a wealth of warning lights that supplement the displays still dot the cockpit. The CRTs hold 26 lines of 51 characters on a 5- by 7-inch screen. That screen size is fairly common on portable computers. However, the number of characters per line is smaller (51 vs. the more common 80) and the number of lines larger (26 vs. the usual 24). The net effect is that the individual characters appear slightly larger on the Shuttle's screens, necessary because although [99] the user of a portable computer is usually about 16 inches from the screen, on the Shuttle the distance between user and screen is well over 2 feet. Information on the Shuttle's screens appears green on black, and characters can be selectively highlighted. Three of these screens are mounted in the forward cockpit between the pilots. A fourth is aft at the mission specialist station. Keyboards, built by Ebonex, are used for crew input. Two are between the pilots, with a third adjacent to the mission specialist's CRT.
Displays placed on the CRTs are controlled by a special-purpose computer with a 16-bit word size and 8K of memory. This computer provides display control and can create circles, lines, intensity changes (highlighting), and flashing messages. The display software is stored on the MMUs until the computer is powered up. The CRT and its associated processor is referred to as the display electronics unit (DEU)58.
Mass Memory Unit: A Late Addition
The final component of the Shuttle's DPS hardware is the mass memory unit (MMU). Originally acquired only to provide initial loading of the orbiter's computers, the MMU, built by Odetics, Inc., has been used extensively to help resolve the memory growth problem. Two of these units are installed on the orbiter, each capable of containing 8 million 16-bit words, enough for three times the Shuttle software. The tape can be addressed in 512 word blocks, and the crew can alter its contents in flight using a special display59. The MMU stores all the Primary Avionics Software System and all the software for the Backup Flight System, the DEUs, and the engine controllers. Thus, the Shuttle continues the same computer/mass memory configuration as the Gemini spacecraft.
This complex network of computer hardware on the orbiter has many possible points of failure. Also, the 700K of flight software may contain undiscovered bugs that could emerge at critical mission times, and self-testing might not be sufficient to protect the spacecraft from such failures. Other schemes for preventing a fatal failure need to be developed if the Shuttle is to fly with the confidence of its crew, passengers, and potential paying customers. Exactly what those schemes would be has occupied many researchers for several years.

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